A circuit for generating a back bias voltage for use in a semiconductor memory device is disclosed, wherein the back bias voltage is clamped within a desired voltage level. The circuit comprises an oscillator for generating a sequence of square waves having a specified frequency, a buffer adapted to be connected with the output of said oscillator and for buffering the output of said oscillator into the square waves having a level of a source supply voltage, a charge pump circuit for providing a back bias voltage by receiving the output of said buffer, and a clamping circuit adapted to be coupled in parallel between the output of said charge pump circuit and a ground level and for clamping within a specified range the back bias voltage being provided by said charge pump circuit in accordance with variations of said source supply voltage.
申请公布号
DE3814667(A1)
申请公布日期
1988.11.17
申请号
DE19883814667
申请日期
1988.04.28
申请人
SAMSUNG SEMICONDUCTOR AND TELECOMMUNICATIONS CO., LTD., GUMI, KR