发明名称 CLOCK INTERRUPTION DETECTION CIRCUIT
摘要 PURPOSE:To save number of monostable multivibrators by constituting the titled clock interruption detecting circuit by the combination of a flip-flop with high circuit integration receiving plural clocks and monostable multivibrators. CONSTITUTION:For example, a clock 1 is given to a data terminal D of a D flip-flop circuit 11 receiving two clocks 1, 2, the clock 2 is given to a clock terminal CK, the clock 2 allows the clock 1 to be held by the D flip-flop circuit (D-F.F circuit) 11 and the interruption of clocks 1, 2 is detected depending whether or not the holding repetitive time is within a time constant of a monostable multivibrator section 12. Thus, number of monostable multivibrators is less and the clock interruption detecting circuit 10 is formed with simpler constitution.
申请公布号 JPS63278414(A) 申请公布日期 1988.11.16
申请号 JP19870112961 申请日期 1987.05.09
申请人 FUJITSU LTD 发明人 KOMATSUBARA HIDEO
分类号 G06F11/00;G06F1/04;H03K5/19;H04L7/00 主分类号 G06F11/00
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