| 摘要 |
PURPOSE:To synchronize a sampling clock with a horizontal synchronizing signal and to reduce the jitter of a sampling by resetting a frequency dividing counter to generate the sampling clock at the timing of an internal horizontal synchronizing signal synchronizing with a reference clock. CONSTITUTION:A reference clock generating means 111 generates the reference clock (j) of a frequency 12 fsc. A synchronizing signal (k) switched by a synchronizing signal switching means 112 is made into the internal horizontal synchronizing signal (l) synchronizing with the (j) by an internal horizontal synchronizing signal generating means 113. A quarterly dividing counter 114 is reset by a reset signal generating means 115 at the signal (l). When the reset is released, the counter 114 quarterly dividing counts the (j), and generates the sampling clock (m). After the initial value (1FA) of an address is set in an address counter 116 at the signal (l) by a load signal generating means 117, the (m) is counted and a picture element address (s) is given to a memory 119 and an input signal (q) selected by an input signal selecting means 107 is A/D-converted at the timing of the (m) by an A/D converting means 118 and a picture element data (r) is recorded in the memory 119. |
