发明名称 DATA TRANSFER CONTROLLER
摘要 PURPOSE:To omit the buffers to be set between the data buses and the local memories and to decrease the hardware quantity by connecting the data buses having the 2<n>-byte widths to the local memories having the 2<n>-byte widths for each corresponding byte unit and designating a local memory and an address to receive accesses based on the main memory address and the data transfer length set when the transfer of data is started. CONSTITUTION:The 2<n> pieces of data buses 100-103 are connected to 2<n> pieces of local memories 20a-20d respectively. A local memory control circuit 30 applies the control signals to the memories 20a-20d to receive accesses successively based on the main memory address and the prescribed transfer length set when the access is started. The circuit 30 also outputs the count pulses for each cycle of the access. A counter 40 gives the access addresses to the memories 20a-20d based on said count pulses. In such a constitution, the buffers can be omitted between those data buses and local memories. Thus the fixed connection is secured between the buses 100-103 and memories 20a-20d, each 2<n> pieces, and the hardware quantity can be decreased.
申请公布号 JPS63279352(A) 申请公布日期 1988.11.16
申请号 JP19870114248 申请日期 1987.05.11
申请人 NEC CORP 发明人 MABUCHI ATSUSHI
分类号 G06F13/28 主分类号 G06F13/28
代理机构 代理人
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