| 摘要 |
PURPOSE:To attain excellent evaluation for the speed margin by giving plural data into a flip-flop in the same timing and storing the data and sending the stored data by a prescribed number each in an optional timing. CONSTITUTION:With a test mode signal T at an 'H' level in evaluating an LSI chip, non-duplicate biphase clocks phi1, phi2 are given to an output buffer simultaneous change number control circuit. Input data signals I11-3m to the output buffer are fetched uniformly in a flip-flop MAR in the timing of the leading of an output buffer enable signal E, an output buffer enable signal goes to 'H' level sequentially from the output buffer simultaneous change number control circuits A1-A3 and the data of the flip-flop MAR are outputted from the output buffer B simultaneously by m-set of data each. Thus, the speed margin is accurately evaluated.
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