| 摘要 |
PURPOSE:To realize stable writing for an address skew with fixing a read/write control signal at LOW by increasing the pulse width of a write inhibit signal generated by a one-shot pulse generated by the occurrence of the variation of an address input more than that of a control pulse. CONSTITUTION:By a circuit 5 which increases the pulse width, the pulse width of the write inhibit signal WI is increased. In this case, each pulse W1 generated by the address A1 and A2 becomes one big pulse of which piling is one. Therefore an inversional pulse between the address skew t1' such as a pulse BLEQ does not exist in an internal write signal WE and memory cell data transitorily selected in the interval of the time of the skew t1' is not inverted by miswriting. Thus without the delay of access time, stably for the address skew, the writing can be executed with fixing the read/write control signal, the inverse of WE at LOW.
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