发明名称 DECODER CIRCUIT
摘要 PURPOSE:To enable the high speed reading motion of a semiconductor memory device by releasing the clamp motion on high level of the output signal of a logical circuit at the changing time of an input signal and overshooting the rise of the output signal of an output circuit. CONSTITUTION:At the changing time of input signals A0, -A0, ..., At-1, -At-1 the motion of a clamp circuit 3 is temporarily stopped, and at this time the high level of the output of a logical circuit 1 is not clamped. Namely, the high level of the output signal Xi of an output circuit 2 is not clamped out becomes of higher level and is restored to a stabilized high level again because the variation in the input signal is temporary. In other words, the signal Xi is subjected to overshooting at the rising time of an output signal Xi.
申请公布号 JPS63279490(A) 申请公布日期 1988.11.16
申请号 JP19870113602 申请日期 1987.05.12
申请人 FUJITSU LTD 发明人 SHIMIZU HARUO
分类号 G11C11/413;G11C11/34;G11C11/408 主分类号 G11C11/413
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