| 摘要 |
PURPOSE:To improve the detection probability of input signals by constituting the titled circuit so that an output signal can not be reset at the time of the transition state of an input signal to a novel peak value. CONSTITUTION:After resetting the circuit, when the output Q of a D-FF 17 is in L-level and Q' is in H-level, a current that flows through a transistor 11 becomes larger than the half of a current I flowing through a constant current source 22. Accordingly, since a current that flowing into a constant current source 25 is in shortage, a current flows from a threshold voltage source VT to the current source 25 by its shortage part of the current. This allows the voltages of the D and R terminals of an FF 17 to be lower than the voltage VT, hence the voltages to to L-level. Even if a clock pulse is inputted to a clock input terminal 8, since the R-terminal of the FF 17 is in L-level, the status of the output Q and Q' do not change, and the resetting is not carried out. Therefore, the peak of an input voltage that leads immediately before the clock pulse can be held. As a result, a reset time can be minimized.
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