发明名称 INFORMATION PROCESSOR
摘要 PURPOSE:To successively secure the contents of a main storage device and to avoid the stop of a system by shifting the contents of the cache memory of memory controller in which a trouble is generated to a normal memory controller. CONSTITUTION:When the trouble is generated in the memory controller 2-1, it is informed to a trouble processor 3-1. The processor 3-1 checks a failure part from trouble information and instructs all discharge to the memory controller 20 because a discharge control is normal at the position of (b) (reading control part of interface). At the position of (a) (discharge control part or interface part), since a discharge operation is not carried out, the cache memory 21 reads for one word unit by an ordinary interface. Writing is executed to the normal cache memory by the ordinary interface to sequentially shift the contents of the memory 21 to the normal cache memory. Thereby, memory data is secured, thereafter, the trouble memory controller is separated to continue an operation.
申请公布号 JPS63278159(A) 申请公布日期 1988.11.15
申请号 JP19870112521 申请日期 1987.05.11
申请人 NEC CORP 发明人 HASHIGUCHI TATSURO
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
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