| 摘要 |
PURPOSE:To obtain an output which is synchronized stably with a signal of up to high frequency by canceling the delay time of an FF which constitutes a synchronizing circuit. CONSTITUTION:A clock pulse from an input terminal 7 is inputted to a D type FF 11 and also inputted to a buffer gate 19 which uses a gate circuit constituting the FF and has a delay time td. A control signal is applied to a data input terminal 6 and the output Q1 of the FF 11 is delayed by a delay time tpd1 after the clock signal is applied to the input terminal 7 and then outputted. Then a clock signal which is delayed a necessary time ts2 behind the inversion of the Q1 output of the FF11 from '0' to '1' is inputted to a terminal CP 2 of a 2nd FF12 and an output which is synchronized with it appears at an output terminal 8. For the purpose, the delay time td is selected to remove the undesired influence of the delay time tpd.
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