| 摘要 |
PURPOSE:To reduce the transmission delay time by adding two transistors(TRs) in a logic circuit comprising a CMOS inverter and a CMOS transfer gate. CONSTITUTION:N-channel MOS TRs Q10, Q2 are added to a conventional EX-OR circuit consisting of input terminals A, B, CMOS inverters 1, 2 and CMOS transfer gates TG1, TG2 as shown in the figure. Through the constitution above, when the input terminal A is at a low level (LL) and an input terminal B is at a high level, an output terminal Y goes to a level HL. In bringing the terminal B to LL in this state, the output terminal goes to a level LL. With the terminal A is at HL and the terminal B at LL next, the output terminal Y goes to a level HL. In bringing the level of the terminal B to HL in this state, the output terminal Y goes to a level LL. Since the logic is progressed by turning ON/OFF the TRs Q1, Q2 without transmission of the signal through the gates TG1, TG2 in this way, the transmission delay time is reduced.
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