| 摘要 |
PURPOSE:To prevent racing of data by providing a required number of stages of inverters retarding a signal passing therethrough between flip-flops forming a scan path so as to avoid the effect of clock skew. CONSTITUTION:Inverters 3, 4 comprising MOSFETs are provided between shift flip-flops 1, 2 comprising MOSFETs. Through the constitution above, a signal at a node D1b is changed with a delay more than a signal at a node D1a. Thus, even in the presence of clock skew retarding a clock signal T2 more than a clock signal T1, since the change in the data at the node D1b is delayed, a data d1 is sent to the node D2 and no racing is caused.
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