发明名称 STATE HOLDING CIRCUIT SCANNING SYSTEM
摘要 PURPOSE:To efficiently and rationally constitute an electronic circuit of large scale by mixing a parallel and serial scan systems in one electronic circuit according to the condition of the quantity of a hardware such as a signal line or a gate line. CONSTITUTION:A scan distribution circuit is provided for the interface circuit of a scan circuit corresponding to respective state holding circuits. In order to apply a scan address to the state holding circuit according to the parallel scan system, a serial/parallel converting circuit is disposed. The address information of serial data steps a shifter counter 10 to decode the value in a decoder 11 and form a parallel scanning address. According to a scan circuit selecting signal formed in a decoder 12, one group of the state holding circuit groups is selected to be scanned. When the selected scan circuit is a serial scan circuit, the address information of inputted serial data is inputted to the relevant serial scan circuit without being converted.
申请公布号 JPS63278149(A) 申请公布日期 1988.11.15
申请号 JP19870112963 申请日期 1987.05.09
申请人 FUJITSU LTD 发明人 AZUMA ISAO;ISHIDA MIYUKI;AOKI NAOZUMI
分类号 G06F11/22;G06F12/06 主分类号 G06F11/22
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