Method and device for regenerating the integrity of the bit rate in a plesiosynchronous system

摘要

The network of the invention comprises, in the transmitter, a "marker" generator which inserts bits of a cyclical sequence into the binary data flow and, in the receiver, a marker processing circuit by which it is possible to identify the start of the marker cycle in order to re-justify the useful data signal in accordance with the detection of this start of a cycle.