| 摘要 |
PURPOSE:To shorten the division operation time by outputting the number of digits of a dividend and that of a divisor by a priority encoder and shifting the dividend in a barrel shifter by the difference of the number of digits and adding/subtracting and shifting the dividend and the divisor thereafter. CONSTITUTION:An output k2 of a priority encoder 6 and an output n2 of an operating circuit 12 are checked by a control circuit 17; and in case of k2=n2, the divisor is 0 and a zero division flag 22 is set. In case of k2=0, the divisor is one and contents of a dividend register B2 are stored in a partial quotient register 10 through a barrel shifter 5 and a partial quotient shifter 8 and 0 is stored in a partial remainder register 9. In case of n2>n, k1<k2 is true and the dividend is smaller than the divisor and the quotient is 0, and 0 is stored in the partial quotient register 10. Contents of the register B2 are stored in the register 9 through a bus B15, the circuit 12, a bus A14, and the partial remainder register 7. Contents of registers A1 and B1 are shifted left in the shifter by bits whose number n2 is stored in a shift count register 4, and they are stored in registers 9 and 10 through shifters 7 and 8. |
