发明名称 MEMORY CIRCUIT
摘要 <p>PURPOSE:To obtain a picture memory having no unnecessary output and to attain a compact IC package by using a memory for recording the (n) picture elements of an effective screen part and a counter having an M cycle operating successively during the period of the recording picture elements. CONSTITUTION:The counter 107 is the counter having the M cycle operating successively during the period of recording the (n) picture elements of the effective screen part. Herein, (n) is defined to be 10 and M to be 6. The two 1H (n picture element) memories of the memories 1 and 2 and alternately used to record the picture elements. A numerical character in a full line indicates a recording address and a numerical character in a broken lines indicates a reading address. When the value of a picture element number 2 is recorded in a 0 address, at the time of reading in the 0 address reading timing of a next line, the second picture element of a preceding line is read, similarly when the value of a picture element number 9 is recorded in a 1 address, at the time of reading in the one address reading timing of the next line, the ninth picture element of the preceding line is read. Accordingly, in this case, he memory operates as a 1H-4D memory. According to the use of such an address control method, address control lines may be a half and the compact IC package can be obtained.</p>
申请公布号 JPS63278182(A) 申请公布日期 1988.11.15
申请号 JP19870113047 申请日期 1987.05.08
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TANAKA TSUTOMU
分类号 H04N19/50;G06T1/60;G06T9/00;H04N19/42;H04N19/423;H04N19/59;H04N19/593 主分类号 H04N19/50
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