发明名称 |
ADDRESS RESPONSE CONTROL CIRCUIT |
摘要 |
PURPOSE:To improve address extension properties by providing a storing means for address space information to the address response control so that the address of an access object circuit can be easily set and added. CONSTITUTION:A storing means 6 receives and stores previously the address space information on an access object circuit 2 from a processor 1. When the processor 1 gives access to the circuit 2 via an address bus 3 and a data bus 4, a decoding means 5 decodes the address received from the bus 3 and at the same time outputs a selection signal 13 to the circuit 2. Then a deciding means 7 compares the address space information on the circuit 2 stored in the means 6 with the address given from the bus 3. Then the means 7 outputs an address response command 29 to an output means 8 as long as the address sent from the bus 3 is included in the address space of the circuit 2. The means 8 outputs an address response signal 9 to the processor 1 by the command 29 and the processor 1 performs the exchange of data to the circuit 2.
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申请公布号 |
JPS63276153(A) |
申请公布日期 |
1988.11.14 |
申请号 |
JP19870111123 |
申请日期 |
1987.05.07 |
申请人 |
FUJITSU LTD |
发明人 |
SHINCHI MICHIHIRO;KOBA MITSUHIRO |
分类号 |
G06F12/02;G06F12/00;G06F12/06;G06F13/16 |
主分类号 |
G06F12/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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