| 摘要 |
PURPOSE:To avoid breakage of the contents of a RAM corresponding to a switched channel even in case a bus error signal is transmitted after a data transfer channel is changed, by adding an operation-only microaddress register MAR to transfer control of a direct memory access DMA. CONSTITUTION:When an exception generating signal like a bus error signal BERR, etc., is supplied from an address register control part 1, the read/write control is given to an operation microaddress register 25 by signals OPR and OPW outputted from the part 1. These signals OPR and OPW are not produced while a data transfer program is processed and then produced when an operating program is processed for bus error processing, etc. Thus the register 25 is controlled. |
