发明名称 TESTING METHOD OF SEMICONDUCTOR DEVICE
摘要 PURPOSE:To make it possible to perform selection at high probability, by obtaining the differences in gate currents, which are measured for the three or more sets of the different gate bias voltages and drain bias voltages of a field effect transistor, and judging the quality of the semiconductor device. CONSTITUTION:At first, gate currents IG for (n) sets (three sets in this example) of drain biases VDSn and gate biases VGSn for a field effect transistor MESFET 2. In this case, VDS1=VDS2=2V, and the step of VGS is made constant as 1V. IG is obtained as IG1, IG2 and IG3 when VGS1=0V, VGS2=-1V, and VGS3=-2V. Then DELTA1=IG2-IG1 and DELTA2=IG3-IG2 are obtained by using the expression of relation of DELTAi-1=IGi-IGi-1 for an integer (i) (2<=i<=n). When the difference between DELTA1 and DELTA2 is DELTA2-DELTA1>0, the FET 2 is judged to be the good product. In this way, the selection can be performed at high probability.
申请公布号 JPS63275966(A) 申请公布日期 1988.11.14
申请号 JP19870110702 申请日期 1987.05.08
申请人 NIPPON TELEGR & TELEPH CORP <NTT> 发明人 WADA YOSHIKI
分类号 G01R31/26;H01L21/338;H01L21/66;H01L29/80;H01L29/812 主分类号 G01R31/26
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