| 摘要 |
PURPOSE:To realize a high-speed access and to prevent the system breakdown even in case of occurrence of a memory fault by switching a data reading destination to a secondary system-memory from a main system memory when the abnormality of the read data is detected by a check system. CONSTITUTION:When a data error is detected by a parity checker 50, the detection pulses S(g) are sent to latches 50 and 51 from the checker 50. Thus the latch 52 is set and a queuing signal is transmitted via a control line 58. Then a CPU 1 is set under a queuing state. At the same time, the latch 51 is also set and a timing circuit 53 is started by a start signal S(f). The circuit 53 sets a gate circuit 54 into a disable state by a main system bus enable signal S(a) so that the read data given from a main system memory 3 is not sent to the CPU 1. Then a secondary system bus enable signal S(c) is sent to a gate circuit 55 and the circuit 55 is set under an enable state. At the same time, a read pulse S(b) is transmitted and a secondary system memory 4 is read out. Then data are put on a data bus 56 via the circuit 55 and sent to the CPU 1.
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