发明名称 SINGLE ERROR CORRECTING MECHANISM
摘要 PURPOSE:To decrease the number of interfaces among LSIs by providing a means transmitting a part of syndrome to all the LSIs including a reception series similarly and an instructing means instructing the presence in a single error of the reception series in an LSI including the reception series individually to each LSI including the reception series. CONSTITUTION:A syndrome generating circuit 13 in an LSI 16 collects all reception series scattered in 4 LSIs to generate a syndrome. A syndrome register 14 is a 6-bit register storing a syndrome signal (o) generated by the circuit 13, and the high-order 3-bit is sent to all the LSIs including the reception series as a bit instruction signal (p). A decoder 15 decodes an LSI instruction signal (q) included in the low-order 3-bit of the syndrome stored in the register 14 and sends the presence of a single error in the LSI as error instruction signals (r), (s), (t), (u) corresponding to each LSI including the reception series. As the LSIs including the reception series, 3rd and 4th LSIs exist in addition to the LSIs 16, 12 and the single error of the reception series is corrected by using a bit instruction signal (p) and the error instruction signal (r-u).
申请公布号 JPS63274220(A) 申请公布日期 1988.11.11
申请号 JP19870106387 申请日期 1987.05.01
申请人 NEC CORP 发明人 ISHIZAKA KOICHI
分类号 H03M13/00;G06F11/10;H03M13/19 主分类号 H03M13/00
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