| 摘要 |
PURPOSE:To attain high speed decoding for an error correction code by detecting error locations being a number less than a number (n) of correctable words by one and calculating the remaining error location based on the error location and a coefficient of an error location polynomial so as to decrease the expected value of the arithmetic operations into (n-1)/n. CONSTITUTION:A value corresponding to n-set of error locations is obtained in the decoding for an error correction code used to correct plural and lots of words such as a BCH code or a reed solomon code used for a recording and reproducing device such as an optical disk or a magnetic disk or the signal transmission. Moreover, an arithmetic section is provided, which adds (n-1)-set of values corresponding to (n-1) error locations obtained by an error location polynomial and coefficients being n-set of addends corresponding to n-set of locations being coefficients of the error location polynomial. Furthermore, (n-1)-set of coefficients corresponding to (n-1)-set of error locations are obtained from the error location polynomial, and coefficients being those of the error location polynomial and n-set of addends corresponding to the n-set of error locations and the (n-1)-set of values are added to calculate the n-th value corresponding to the n-th error location. Thus, the calculation time of the error locations is shortened and the decoding of the error correction code is quickened.
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