发明名称 DRAM SENSE REFRESH CIRCUIT
摘要 PURPOSE:To maintain the symmetry of a load capacity separating the large capacity of a bit line from an input at the time of starting a sense operation. CONSTITUTION:A reference voltage inputted to the other input part 4 of a differential sense amplifier is generated by dividing resistances 38, 39. The connecting point of the resistances 38, 39 is connected to the other input part of the differential sense amplifier through a transfer gate 29, a transistor 20 is serially inserted between the resistance 29 and an earth voltage terminal and a current passing through the resistances 38, 39 when a timing signal phiREF impressed to the gate of the transistor 20 goes to a low level is interrupted. Namely, at the time of starting the sense operation, the bit line and a reference voltage generating circuit are separated from the input part of a sense amplifier and only the capacity of the input part of the sense amplifier goes to the load capacity. Thereby, the balance of the capacity can be obtained without dividing the bit line into two at both the side of the differential sense amplifier and connecting.
申请公布号 JPS63275092(A) 申请公布日期 1988.11.11
申请号 JP19870111067 申请日期 1987.05.07
申请人 MATSUSHITA ELECTRONICS CORP 发明人 HATTA MINORU
分类号 G11C11/409;G11C11/34 主分类号 G11C11/409
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