| 摘要 |
PURPOSE:To realize the connection between two units which prescribed the high performance timing while maintaining the interchangeability with the existing units, by switching 1st and 2nd clock signals with each other in response to a clock specifying signal and supplying those clock signals to a data processing unit. CONSTITUTION:When a unit 1 transfers data with a unit 2, a bus control circuit 11 activates a drive circuit valid signal 111 and at the same time sets a timing designating signal 112 at 1. A drive circuit 13 outputs the signal 112 to a timing mode signal line 41. Thus a signal is supplied to a data control circuit 12 from a 1/2 cycle clock signal line 43 via gates 14-4 and 14-5 together with a signal supplied to the circuit 12 from a 1/4-cycle clock signal line 44 via gates 14-7 and 14-8 respectively. The signals are always supplied to a data control circuit 22 in the unit 2 from both lines 43 and 44. Thus data are transferred smoothly between both units 1 and 2 in a short clock cycle mode.
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