| 摘要 |
PURPOSE:To eliminate multiplexing and speed conversion circuits by disposing communication memories at every time division highway of each speed and disposing one holding memory which controls the reading of respective communication memories for respective communication memories in common. CONSTITUTION:Data of the input highways HWi0-HWi2 are sequentially written in the communication memories SPM0-SPM2 at the speed of respective input highways. A communication memory number and the address of the communication memory are written in the content of the holding memory HM as connection information of a pass. Consequently, designated addresses of the designated communication memories are sequentially read and outputted to an output highway HW0 in accordance with the content of the holding memory. Here, the speed of the output highway HW0, namely, the read speed of the holding memory HM can optionally be set. Thus, the multiplexing and speed conversion circuits are eliminated.
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