发明名称 HOLDING CIRCUIT FOR PARITY CHECK DETECTION DATA
摘要 PURPOSE:To supply a parity check detection data to a protecting circuit without missing at the time of inputting a frame pulse by feeding the output of a D flip-flop circuit to store the parity check detection data. CONSTITUTION:The parity check detection data is supplied to an OR circuit 12, and when the result of parity shows dissidence, the output of level 1 is fed back to a terminal D from an output section of a D flip-flop circuit 13 and the level of the loop is always kept to logical 1. The flip-flop circuit 13 latches the data till the next frame pulse FP is supplied to an AND circuit 11 and when the frame pulse FP to the AND circuit 11 again supplied after the result of parity check is coincident, the flip-flop circuit 13 is reset. Thus, the parity check detection data is fed to protecting circuit without missing of bits.
申请公布号 JPS63273139(A) 申请公布日期 1988.11.10
申请号 JP19870107192 申请日期 1987.04.30
申请人 FUJITSU LTD 发明人 SASAKI YOSHIHITO;NAKAMURA SHINICHI
分类号 G06F11/10;H04L1/00 主分类号 G06F11/10
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