| 摘要 |
PURPOSE:To lower collector capacity and emitter capacity so as to improve high-speed performance and to facilitate the formation of IC, by forming an emitter or collector region so as to contact with an outer base region on their sides and forming an intrinsic base region on a region which includes a boundary between the emitter or collector region and the outer base region. CONSTITUTION:An emitter region 33E or a collector region is formed to contact with an outer base region on their sides, and an intrinsic base region 38B is formed on a region which includes a boundary between the emitter region 33E or collector region and the outer base region 36b, and a collector region 39C or an emitter region is formed on the intrinsic base region 38B. For example, selective etching of a slanting composition layer 34 and an N-Al0.3Ga0.7As layer 33 is performed to form the emitter region 33E, and next p<+>-GaAs layer 36 serving as the outer base region is made to selectively grow. In succession, a p<+>-GaAs layer 38 serving as the intrinsic base region, an n-GaAs layer 39 serving as the collector region, and the like are made to grow serially by a MOCVD method. Subsequently, an RIE method is used to perform selectively etching removal of the n-GaAs layer 39, the p<+>-GaAs layers 38, 36, and the like.
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