发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PURPOSE:To obtain the low power consumption by increasing and decreasing the bias current of a source follower or an emitter follower circuit with a control signal to delay the output signal of the circuit. CONSTITUTION:In an emitter follower circuit, an NMOS101 constitutes a bias current source and a circuit 200 composed of a resistance 102 and a capacity 103 constitutes a delay circuit. By delaying the voltage of an output terminal 2 with a CR delay circuit 200 and impressing it to a gate terminal 5 of the NMOS101, the bias current is increased and decreased. The bias current activates so as to decrease at the time of charging and driving a load and to increase at the time of discharging and driving it. Accordingly, a reactive current part is decreased at the time of charging and driving, the driving current of a driving transistor is efficiently used to the driving of he load, a speed performance is improved and under the design of constant power consumption, an active current is increased only with the decreased reactive current part. Thus, the speed performance of the circuit can be improved.
申请公布号 JPS63272109(A) 申请公布日期 1988.11.09
申请号 JP19870104247 申请日期 1987.04.30
申请人 HITACHI LTD 发明人 SUZUKI MAKOTO;HIGUCHI HISAYUKI
分类号 G11C11/413;G05F3/16;G11C11/34;H03F3/34;H03F3/345;H03F3/50;H03K5/003;H03K19/0175 主分类号 G11C11/413
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