| 摘要 |
<p>Last-in, first-out buffers (100, 106) contain a position indicating that a character is the last one of a packet. In this way, a user need not monitor reception or transmission on a character-by-character basis, but need only concern themselves with packets. The receive and transmit FIFO's generate requests for more characters by monitoring the number of characters stored and thereby automatically receive and transmit characters without processor intervention. A four-stage mechanism (600,602,604,606,608,610,612,614) permits monitoring of multiple contiguous frames (back-to-back frames) received. Control of the DLC is provided by status and control registers (112,212) which are accessible to the user via a microprocessor interface (50). Particular registers have bit positions monitoring status conditions in such a manner that the most-probable one of a set of conditions compries the least-significant bit position, while the least-probable condition occupies the most-significant bit position. This afford simple shift and test technique for monitoring status conditions.</p> |
