| 摘要 |
PURPOSE:To form a PLA high in density in an RAM area by including the PLA formed in a memory area composed of plural first basic unit circuits and plural second basic unit circuits having an input line to extend approximately vertically to the output line extending in one direction, respectively. CONSTITUTION:An MOS gate array device has a PLA formed in a memory area composed plural first basic unit circuits 40 and plural second basic unit circuits 41. In the first basic unit circuits 40, a pair of metal wiring layers are formed as a pair of output lines 11 and 12 of the PLA approximately at a right angle to an input line 12. The output lines 11 and 12 are equivalent to the pair of the bit lines of an SRAM circuit. In the second basic unit circuits 41, a metal wiring layer as a pair of input lines 10 and 11 linked to the gate of NMOS transistors N2 and N3 is formed at a right angle with the output line 12. The input lines 10 and 11 are equivalent to the bit line of the SRAM circuit. Thus, the PLA can be formed high in density in the RAM area.
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