发明名称 Data transfer controlling apparatus for direct memory access.
摘要 <p>A data transfer controlling apparatus for direct memory access comprising one or more first microaddress registers (40-43), each of which stores microaddress information for program processing the data transfer for a corresponding channel; a second microaddress register (45) which stores microaddress information for program processing other than the program processing the data transfer; a micro read only memory (7) operatively connected to the first (40-43) and second (45) microaddress registers, for storing microinstructions and outputting a predetermined microinstruction in accordance with microaddress information read out from a selected one of the first microaddress registers (40-43) or the second microaddress register (45); and an incremental element (6) operatively connected to the first (40-43) and second (45) microaddress registers, for incrementing the value of the microaddress information read out from the selected one of the first microaddress registers (40-43) and the second (45) microaddress register and for writing the incremented microaddress information to the selected one of the first microaddress registers (40-43) and the second (45) microaddress register. The microaddress information stored in the first microaddress registers for the corresponding channel is read out when program processing data transfer for the corresponding channel is carried out, the microaddress information stored in the second microaddress register (45) being read out when program processing other than the said program processing of data transfer is carried out.</p>
申请公布号 EP0290256(A2) 申请公布日期 1988.11.09
申请号 EP19880304065 申请日期 1988.05.05
申请人 FUJITSU LIMITED;FUJITSU MICROCOMPUTER SYSTEMS LIMITED 发明人 TANIAI, TAKAYOSHI;SAITOH, TADASHI;FUJIHIRA, ATSUSHI
分类号 G06F9/26;G06F13/28 主分类号 G06F9/26
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