| 摘要 |
<p>PURPOSE:To obtain a frame synchronizing circuit capable of performing a fast operation, by constituting a circuit in such a way that the delay time of a loop circuit can be shortened as far as possible by incorporating a mismatch circuit and a count stop circuit in a counter circuit and inserting a gate to the data input of a D-type FF. CONSTITUTION:The frame synchronizing circuit is constituted fundamentally as a shift register with (n) (for example, four)-stages in which (n) (for example, five) FFs 7-11 are cascade-connected, and the outputs E of first (n-1) (for example, four) FFs 7-10 are fed back to the FF7 at a first stage. The gates 14-17 equivalent to the detection of the mismatch and the stoppage of count are inserted between an FF11 which generates a frame position pulse F and the FF at the next stage, and between the FF11 and the FF at a preceding stage. In such a way, input data latched at an FF6 is operated in parallel by separating it to data for protecting synchronism and the one for hunting, thereby, the delay time of the loop circuit can be shortened as far as possible. Therefore, the fast operation with a short frame period recovery time can be realized even when a clock frequency is raised.</p> |
