| 摘要 |
PURPOSE:To output an output clock signal synchronizing with a digital signal, by supplying the output of the variable oscillator of an analog PLL to a digital PLL as a reference clock signal, and supplying the digital signal(EFM). CONSTITUTION:A second clock signal VCO can be obtained by supplying a first clock signal from the analog PLL1 to the digital PLL 11. The PLL11 is constituted of a circuit 13 which detects the phases of the digital signal and the second clock signal VCO, and a digital filter 17 to which the comparison output of the above signals is supplied, and a phase modulation circuit 26 to which the output of the filter is supplied. Since the circuit 26 is provided with a variable base number counter 30, it is synchronized with the digital signal when it is a PWM signal, and the clock signal VCO having the clock frequency can be obtained easily. Also, it is possible to heighten the frequency accuracy of the signal VCO even when the frequency of the clock signal to be supplied to the PLL11 is low. |
