发明名称 |
Semiconductor memory device having redundancy configuration with read circuit for defective memory address |
摘要 |
A semiconductor memory device having a redundancy configuration including a read circuit for a defective memory address. The read circuit includes a transistor which forms a current switch circuit with a bipolar-transistor of an input buffer circuit. The base electrode of the transistor is connected to the output terminal of a PROM which stores a defective address. The reading operation is carried out by applying a voltage lower than a normally applied voltage to the base electrode of the bipolar-transistor and detecting the base current. |
申请公布号 |
US4783781(A) |
申请公布日期 |
1988.11.08 |
申请号 |
US19860883756 |
申请日期 |
1986.07.09 |
申请人 |
FUJITSU LIMITED |
发明人 |
AWAYA, TOMOHARU |
分类号 |
G11C11/40;G06F12/14;G11C29/00;G11C29/04;G11C29/18;(IPC1-7):G06F11/20 |
主分类号 |
G11C11/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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