| 摘要 |
PURPOSE:To execute arbitrary bus arbitration from a master processor to a slave processor by providing the master processor with a bus preferential use signal output means and providing the slave processor with a bus occupation signal output means. CONSTITUTION:When a master processor 10 allows a slave processor 21 to use a main bus 30, a bus preferential use signal BGS1 is set to the high level and an input terminal EN of a bus gate 41 goes to the high level, and the main bus 30 is connected to a local bus 51, and an input terminal BGIN1 of the slave processor 21 goes to the high level to report to the main bus usable state. When the bus preferential use signal BGS1 is set to the low level, the input terminal EN of the bus gate 41 goes to the low level, and the main bus 30 and the local bus 51 are released, and the input terminal BGIN1 of the slave processor 21 goes to the low level to report the main bus use inhibiting state. |
