| 摘要 |
PURPOSE:To share the PLL circuit of a decoding part in respective mode times by generating a memory control clock in the PLL circuit of the decoding part of the post stage of a memory at the time of the W mode and in the PLL circuit for locking a horizontal synchronization at the time of the R mode. CONSTITUTION:A composite video signal is written in a main memory 102 through an A/D converter 101. During the W period, a signal equivalent to a video signal input from an input terminal 401 is inputted to the decoding part 4 and accordingly, a signal from a PLL oscillating means 405 in the decoding part 4 is synchronized with a burst signal in the input signal in phase. This signal is supplied to the memory part 1 as a clock through a frequency multiplier 31. During the R period, a sub-carrier form a clock generating part 3 is supplied to the memory part 1 and a printer part 6 as the clock through the frequency multiplier 31. |
