SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PURPOSE:To obtain an integrated circuit provided with a sub-boosting circuit having of a high boosting efficiency by setting the absolute value of the threshold voltage of a first MOS transistor TR lower than the threshold voltage of a second MOSTR, and obtaining a boosted output from the output terminal of a selection circuit. CONSTITUTION:A boosted output VPP from a main boosting circuit 11 is supplied to the sub-boosting circuit 12 and a circuit 13 to be supplied. The circuit 12 consists of N-channel type MOSTRs Q1, Q2 and a MOST capacitor C1, and the gates are connected to the selection circuit 14. To the source of the TR Q1, the drain and the gate of the TR Q2 are connected, and to the source of the TR Q2, a node N1 is connected. To the connection point of the source of the TR Q1 and the drain and the gate of the TR Q2, one electrode of the capacitor C1 is connected, but to the other electrode of the C1, a clock pulse phiC from a clock generation circuit 15 is supplied. The circuit 13 comprises an N-channel type MOSTR Q3, and to the drain of the TR Q3, the output terminal of the circuit 11 is connected. By setting the absolute value of the threshold voltage of the TR Q1 lower than the threshold voltage of the TR Q2, the output potential of the circuit 12 can be boosted.