发明名称 ACCESS CONTROL CIRCUIT FOR DRAM
摘要 PURPOSE:To execute a read/modify/write action over consecutive two bits by adding a shift starting position control part and a shift range control part for consecutive two bits to a nibble shift register of four bits. CONSTITUTION:Based on a nibble address of lower two bits supplied to the shift starting position control part 12, one output terminal of a decoder D goes to H-level, and the output of a gate G1 goes also to H-level. This causes a selection signal Y1 from an FF11-1 to turn to H-level to read a data from a memory cell block M1. At this point of time of said reading, an L-output from the FF11-1 is sent to a gate G2 to read a from a memory cell block M2. At the ending time of this read, a selecting signal SEL goes to H-level, and a data-write to the block M2 is executed. In such a way, a signal SEL is shifted to H-level only at the ending time of a second-bit read in order to re-set on FF in the precedent stage, thus a read/modify/write action over two bits is executed.
申请公布号 JPS63268187(A) 申请公布日期 1988.11.04
申请号 JP19870101230 申请日期 1987.04.24
申请人 NEC CORP 发明人 KATO AKIRA
分类号 G11C11/401;G06F12/02;G06F12/06;G11C11/34 主分类号 G11C11/401
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