| 摘要 |
PURPOSE:To reduce the load of an input/output bus and an input/output controller by using a cyclic sequence number and an answer request flag in order to omit a process where the occurrence of an error is reported to the input/ output controller when no writing error is produced to a main memory means. CONSTITUTION:When an access request is given to a main memory 2 from an input/output controller 4, a bus control part 14 generates an answer request flag to show whether a cyclic sequence number (S) and the return of an answer should be requested or not and stores this flag into a request buffer memory part 12. When the output is possible for the information stored in the part 12, the part 14 secures an input/output bus 6 to send the address of the controller 4 to the bus 6 as the address information as well as the error information and an S signal as the data information respectively. The controller 4 detects that its own address is sent to the bus 6 and fetches the data on the bus 6 to know a specific access request of the number S is over normally or abnormally. Then a process where an access request is reported to the controller 4 when said request is over normally.
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