| 摘要 |
PURPOSE:To decrease a circuit scale by providing a pulse conversion means converting an output of a prescribed AND means into an output pulse synchronously with a clock and a reset pulse. CONSTITUTION:A clear pulse is fed to CL terminals of a FF 61 and a reset/set latch(RS) 41 whose S, R terminals receive a level 1 at first in a pulse width converting circuit to clear them, then a Q terminal of the RS 41 goes to 0. While no pulse is given, an output of an AND gate 51 goes to 0, the level of the Q terminal of the FF 61 goes to 0 and the output of the Q goes to 1. When a pulse is given, the Q terminal of the RS 41 goes to 1, and the output of the AND gate 51 goes to 1, then the output of the Q terminal of the FF 61 goes from 1 to 0 by a clock (a) and the output of the AND gate 51 goes also from 1 to 0. With no pulse given to the RS 41, the Q terminal goes to 1 and the state is restored to the initial state, but when the pulse is inputted, the above-mentioned operation is repeated.
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