发明名称 HOLD METHOD FOR MULTI-STAGE PROTECTION CIRCUIT
摘要 <p>PURPOSE:To eliminate need for a distribution circuit even if the number of stages of a multi-stage bistable means increased by using an output of a hold control means so as to hold only a 1st stage bistable means to a prescribed state. CONSTITUTION:When a subscriber side completes the transmission of data and the power supply is turned off, a hold control means 42 uses a hold signal and an output signal from an output signal generating means 6 to generate a control signal controlling the operating state of the 1st stage bistable means 51 to hold the 1st stage bistable means only to a prescribed state by this control signal. Thus, the output state of the 1st stage bistable means is shifted sequentially toward the post-stage by using the inputted clock and the entire multi-stage bistable means 5 is held to this state and the output signal is held attained therewith.</p>
申请公布号 JPS63266938(A) 申请公布日期 1988.11.04
申请号 JP19870100703 申请日期 1987.04.23
申请人 FUJITSU LTD 发明人 WATANABE OSAMU
分类号 H04M3/24;H04J3/06;H04L7/08 主分类号 H04M3/24
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