HIGH SPEED LOW PIN COUNT BUS INTERFACE

摘要

Bus interface apparatus is provided to drive a high speed bus (67) with two nonoverlapping clock signals (C34/C61). The apparatus takes advantage of the inherent bus capacitance which will temporarily hold data signals placed on the bus by using bus interface circuitry having high input and output impedances. That circuitry can thus be activated by coincident signals (C34, C61).