| 摘要 |
For registers which can be connected both to individual data sources (IOP) and to a common data source (CPU/SVP), and for which only one control connection for common switching of all the registers is available for switching to the common data source, the control signal (TF) which causes the switching is linked to two successive control cycle pulses (CLA and CLB), with a time separation between them, of which only one causes the switching and the acceptance of the data of the common data source (CPU/SVP) into the selected register (EW). If the first control cycle pulse (CLA) coincides with a request from the individual data source (IOP), the latter is handled first, and only the second control cycle pulse (CLB) is effective. Otherwise, the first control cycle pulse (CLA) is always effective, and a subsequently incoming request (I.STROBE) from the individual data source (IOP) is only executed after the end of the first control cycle pulse (CLA). <IMAGE>
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