| 摘要 |
<p>In a memory circuit including a write bit-line (32, 36) for writing data into a memory cell (10), and a read bit-line (34, 38) for reading data from the cell, a transistor (50, 52) is included, connected with the write bit-line and the read bit-line, so that when a fast flush signal is applied by an AND gate (44) to the gate of that transistor, direct connection is made between the write bit-line and read bit-line, so that data is written into the cell, but can be read simultaneously from the read bit-line, reducing the fall-through delay.</p> |
