| 摘要 |
PURPOSE:To shorten the response time of a DMA (Direct Memory Access) controller and to reduce the load on a CPU by providing plural operation request input terminals for each channel and performing different data transfer operation according to a device which requests the operation. CONSTITUTION:Plural operation request input terminals 24a-24d are provided for each channel of a DMA controller 2, and pointers (registers) 25a-25d are provided in the DMA controller 2 corresponding to the respective operation request input terminals 24a-24d. Corresponding address (table reference address) on a memory where transfer information such as a DMA transfer command and the head address of a transfer origin and a transfer destination is stored as a table are set in those pointers 25a-25d. Consequently, the simple system constitution which does not require any interruption controller shorten the time from the acceptance of a request by the DMA controller 2 to the start of the data transfer operation, i.e. the response time of the DMA controller 2. |
