发明名称 Address generating circuit.
摘要 An address generating circuit (13) generates a reading address for reading a buffer memory (16) so that so-called P and Q codes for a CD-ROM which have parameters i and j can be decoded. The reading address is obtainable based on a formula RDA = H + 2L + p, where H is a starting address of one block not including synchronous signal or pattern, L is a symbolic location of a symbol, and p is a sign for designating that the symbol is included in an LSB byte plane or an MSB byte plane. A first full adder (25) operates the symbolic location L based on the parameters i and j with various constants being given from a constant generator (23) so as to give the symbolic location L to a second full adder (21). The starting address H is given from a writing address pointer (12a). The second full adder makes an operation for adding H, 2L and p to output the reading address to an address bus. In addition, the symbolic location L is latched in a symbol off-set address (26) and, if necessary, fed-back to the first full adder through multiplexers (24, 27) when the next symbolic location is to be operated.
申请公布号 EP0288989(A2) 申请公布日期 1988.11.02
申请号 EP19880106726 申请日期 1988.04.27
申请人 SANYO ELECTRIC CO., LTD. 发明人 TOMISAWA, SHIN'ICHIRO
分类号 H03M13/00;G11B20/10;G11B20/18;G11B27/30 主分类号 H03M13/00
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