| 摘要 |
PURPOSE:To miniaturize and highly integrate a chip by effectively utilizing a bonding pad area in a semiconductor of IC or LSI, etc., by forming an element region for an element evaluation test not used after a functional circuit is completed on a semiconductor region directly under an external connection terminal. CONSTITUTION:A testing circuit 8 is to perform an element evaluation test for a malfunction analysis after forming an element region 2 for an IC function circuit on the surface of an Si wafer 1. In the test, it is so exposed as to draw only the pattern of the circuit 8. After the test is finished, it is covered thereon with an insulating film, pads are formed, and a chip surface is covered with a passivation film 6. After a semiconductor chip is completed, the pads are used for wire bonding, but the circuit 8 under the pads is no longer used. Thus, a semiconductor region under the pads not heretofore used can be effectively utilized in the chip without considering the impact of bonding to the pads. |
