发明名称 MANUFACTURE OF MULTILAYER INTERCONNECTION IN SEMICONDUCTOR DEVICE
摘要 PURPOSE:To enable the forming of a multilayer interconnection which is small in its cost and high in its productivity, by using chemical etching means which are applicable to a resist film and a first interlayer film, respectively, without using an RIE method and next by flattening the first interlayer film. CONSTITUTION:A SiO2 film 12 is formed as a first interlayer film so as to cover an Al wiring 11. A low viscosity photoresist 13 is formed on a substrate. Subsequently the substrate is provided with a proper baking process, and next a developing solution with organic alkali, e.g., TMAH ((CH3)4N+OH<->) contained as its basic element is dripped on the substrate. When the substrate is rotated and the SiO2 film 12 on the Al wiring 11 is exposed, resist etching is finished. The substrate is provided with a baking process, for example, at 140 deg.C and an etchant for SiO2 (for example with hydrofluoric acid contained as a basic element) is used to expose the SiO2 film 12 on the Al wiring and remove it by etching, so that the surface of the SiO2 film 12 is flattened. Subsequently the resist film 13 remaining on the SiO2 film 12 between wirings is removed to form a SiO2 film 14 as a second interlayer film, and a second layered Al wiring 16 is formed on the film 14.
申请公布号 JPS63265447(A) 申请公布日期 1988.11.01
申请号 JP19870101028 申请日期 1987.04.23
申请人 TOSHIBA CORP 发明人 NAGAMATSU TAKAHITO;OKUMURA KATSUYA;ARAKI TOSHINOBU
分类号 H01L21/302;H01L21/3065;H01L21/3205 主分类号 H01L21/302
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