| 摘要 |
<p>An OR-AND logic circuit includes a plurality of OR gates wherein each OR gate includes a plurality of source coupled FETs and the inputs to each OR gate are the control gates of the FETs. A logic node serves as the output for each OR gate. A unidirectional current conducting means, such as a Schottky diode, is connected to each output logic node of each OR gate. One terminal of each unidirectional current conducting means is connected to a common logic node. Current passing through a load means passes through the common logic node and is divided among the unidirectional current conducting means so that a logical AND function is provided at the common logic node with the logic condition at the output logic nodes of the OR gates serving as the inputs to the AND gate. Multiple levels of such OR-AND circuits can be provided with the AND output of one level serving as the input to an OR gate of the next stage.</p> |
