发明名称 |
PROCESS FOR FORMING PLANAR CHIP-LEVEL WIRING |
摘要 |
<p>Disclosed is a process of forming high density, planar, single- or multi-level wiring for an semiconductor integrated circuit chip. On the chip surface is provided a dual layer of an insulator and hardened photoresist having various sized openings (grooves for wiring and openings for contacts) therein in a pattern of the desired wiring. A conductive (e.g., metal) layer of a thickness equal to that o. the insulator is deposited filling the grooves and contact openings. A sacrificial dual (lower and upper component) layer of (hardened) photoresist is formed filling the metal valleys and obtaining a substantially planar surface. The lower component layer is thin and conformal and has a higher etch rate than the upper component layer which is thick and nonconformal. By reactive ion etching the sacrificial layer is removed leaving resist plugs in the metal valleys. Using the plug as etch masks, the exposed metal is removed followed by removal of the remaining hardened photoresist layer and the plugs leaving a metal pattern coplanar with the insulator layer. This sequence of steps is repeated for multilevel wiring. When only narrow wiring is desired, a single photoresist layer is substituted for the dual photoresist sacrificial layer.</p> |
申请公布号 |
CA1244145(A) |
申请公布日期 |
1988.11.01 |
申请号 |
CA19870529470 |
申请日期 |
1987.02.11 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BALASUBRAMANYAM, KARANAM;DALLY, ANTHONY J.;RISEMAN, JACOB;OGURA, SEIKI |
分类号 |
H01L21/3205;G03F7/09;H01L21/027;H01L21/302;H01L21/3065;H01L21/768;(IPC1-7):H01L21/72 |
主分类号 |
H01L21/3205 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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